Semiconductor memory manufacturing technology allows the creation of high density memory arrays on an integrated circuit chip. Such memory arrays consist of many memory cells, each cell capable of storing one data bit.
A dynamic random access memory (DRAM) includes an arrangement of such memory cells. Each memory cell comprises a storage capacitor for storing a data bit as a charge and an access transistor for accessing the charge. The data bit charge provides either a binary logic high (high) voltage or a binary logic low (low) voltage. Data is stored in the memory cells during a write mode and retrieved during a read mode. The data is transmitted to and from the memory cells on signal lines, referred to as bit lines or digit lines. The digit lines are coupled to input/output (I/O) lines through I/O transistors used as switches. Each memory cell provides, through a true digit line, the logic state of its stored data bit to a corresponding I/O line. Each memory cell also provides, through a corresponding complimentary digit line, the complementary logic state of its stored data bit to a corresponding I/O complement line. The true digit line and corresponding complimentary digit lines are referred to collectively as a digit line pairs.
The memory cells are typically arranged in an array and each memory cell has an address identifying its location in the array. The array comprises a configuration of intersecting rows and columns. A memory cell is associated with each intersection. In order to read from or write to a memory cell, that memory cell must be selected, or addressed. A row decoder activates a word line in response to a specified row address. The activated word line turns on the access transistors for each memory cell of the row. A column decoder selects a digit line pair in response to a specified column address. For a read operation the selected word line activates the access transistors for all memory cells in the row, and the column decoder couples the data of a particular memory cell onto a corresponding digit line pair.
As set forth above, DRAM memory cells use storage capacitors to store data. A logical high, or logical "1", is stored as a charge on the capacitor. The capacitor is discharged for a logical low, or logical "0". Digit line pairs are fabricated as metal lines on the integrated circuit and connected to the memory cells for communicating data stored in the memory cells.
For reading data, the digit line pairs are first equilibrated to the same voltage. Charge from a particular memory cell is coupled, for example, onto a true digit line, resulting in a small differential voltage between the true digit line and its corresponding complimentary digit line. A sense amplifier senses the small differential voltage across the digit line pair, and further increases the voltage differential to full logic levels for communication to the corresponding I/O lines.
To obtain faster circuit operation, there is a need for sense amplifiers that reduce the time required for reading data from a particular memory cell. For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for faster sense amplifiers.